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맞춤 설계 서비스
SoC Solution
고객의 우수한 제품 경쟁력 확보를 위해, 자체 차별화 설계 솔루션과 파트너 사와의 맞춤 설계서비스, 인프라 솔루션을 기반으로,
Spec-off부터 통합, 물리적 구현, 검증까지 다양한 분야에서 맞춤 설계 서비스를 제공하고 있습니다.
Design Service Flow
Flow
- SPEC
- Architecture Definition
- SoC Design Verification
- Prototyping & Validation
- SoC Implementation
- Evaluation Board &
S/W Setup
- SoC EV Test
- SoC Production(SCM)
- System Design
- System Production
Flow
- SPEC
- Architecture Definition
- SoC Design Verification
- Prototyping & Validation
- SoC Implementation
- Fab-in
- Fab-out
- Package
- SoC EV Test
- SoC Production(SCM)
- System Design
- System Production
Design Service Flow
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Spec |
RTL |
Synthesis |
DFT |
Auto P&R |
Physical Verification & PSI Vertification |
Test Vector & Failure Analysis |
Maintenance |
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Lv.2 |
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High Performance
Physical Implementation
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- Hardening for Computing Clusters
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- Physical & Power-aware Logic Synthesis
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- Logic Synthesis with physical information and power scenario
- Placement-Aware Multi-Bit Resister Banking
- Physically aware Clock Gating restructuring
Design for Testability
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- Support-advanced DFT Solutions
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- Low pin count test with serializer
- Power Aware DFT
- Test Fail Diagnosis
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- Memory BIST(Build-in Self Test)
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- Memory BIST/BIRA for higher SRAM yield
- Repair solution with eFuse & OTP
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- Logic BIST
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- Hardware based in-field testing method
- On-chip generated random patterns for safety and mission critical applications
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- In-System test
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- For safety-critical applications such as automotive, aerospace and medicine
- Use IST(In-System Test)controller through IJTAG network
- To access the chip during operation
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- Scan(Advanced DFT skill)
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- Scan test for improved test coverage for lower DPPM
- Stuck-At, Bridge, Transition, Path-delay, OCCT, Burn-in
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- Boundary Scan
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- Inter-chip connection test method for system level testing
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- Physical DFT consider
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- Physical Reordering and Repartitioning
Physical Design
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- Accurate and robust timing analysis
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- LVF based variability library
- Moment-based LVF to cope with non-Gaussian effect
- Parametic OCV method
- CCS/CCSN-based STA
- Statistical Rvia STA
- NP-Skewed corner STA for hold timing, min-pulse, and DCD check only
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- Physical Optimization
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- BEOL-aware delay optimization(BEOL resistance increase impacting path delay)
- Mixed DDB/MDB Flow
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- Physical-aware Timing ECO
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- Minimize physical side-effect for ECO
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- MIM-aware Timing ECO
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- Produce a single ECO file for Multiply Instantiated Module
- Accelerate multi-core CPU/GPU timing closure
Low Power
Dynamic Power Optimization
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- Multi-supply Voltage&Voltage Island
- In-Ruch Current prevented power gating
- Clock/Memory-Gating
- Dynamic Voltage Frequency Scaling
- Vector-Driven Optimization
- Decap pre-placement method
- Merge or split ICG/Multi-bit flip-flop
- LowPower CTS(Concurrent Clock and Data Optimization)
Leakage Power Optimization
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- Multi-Vth Optimization
- Gate-Length Biasing
- Sign-off Leakage Optimization
Low Power Verification
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- Low power static rule check
- Power-aware Somulation
- Power-aware equivalence check
Power & Signal Integrity
Power Integrity Solution
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- Power Plan based on Early Prototyping Analysis
- Dynamic Voltage Drop Analysis
- Static Power Analysis
- Power EM/BUMP Current
- P/G Resistance check
Signal Integrity Solution
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- Signal EM
- Glitch Noise analysis
- Clock Jitter validation
- Duty-cycle distortion methodology
- Clock Propagation Check
- 3-row decap inverter on CTS
- Semiconductor Global Top Tier Design House, SNST KOREA
- Semiconductor Global Top Tier Design House, SNST KOREA