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Custom Design service

SoC Solution

SNST delivers end-to-end custom SoC design services—from spec-off to system integration, physical implementation, and verification.
Built on proprietary design expertise, customer-specific design engagements with industry partners,
and infrastructure solutions, we help clients gain a competitive edge in semiconductor innovation.
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Design Service Flow

    Flow

    • SPEC
    • Architecture Definition
    • SoC Design Verification
    • Prototyping & Validation
    • SoC Implementation
    • Evaluation Board &
      S/W Setup
    • SoC EV Test
    • SoC Production(SCM)
    • System Design
    • System Production

    Flow

    • SPEC
    • Architecture Definition
    • SoC Design Verification
    • Prototyping & Validation
    • SoC Implementation
    • Fab-in
    • Fab-out
    • Package
    • SoC EV Test
    • SoC Production(SCM)
    • System Design
    • System Production

Design Service Flow

Spec RTL Synthesis DFT Auto P&R Physical Verification & PSI Vertification Test Vector & Failure Analysis Maintenance
Lv.0
Lv.1
Lv.2
Lv.3

High Performance

Physical Implementation

  • Hardening for Computing Clusters
    • CPU
    • NPU
    • GPU
    • Hash Core
  • Physical & Power-aware Logic Synthesis
    • Logic Synthesis with physical information and power scenario
    • Placement-Aware Multi-Bit Resister Banking
    • Physically aware Clock Gating restructuring

Design for Testability

  • Support-advanced DFT Solutions
    • Low pin count test with serializer
    • Power Aware DFT
    • Test Fail Diagnosis
  • Memory BIST(Build-in Self Test)
    • Memory BIST/BIRA for higher SRAM yield
    • Repair solution with eFuse & OTP
  • Logic BIST
    • Hardware based in-field testing method
    • On-chip generated random patterns for safety and mission critical applications
  • In-System test
    • For safety-critical applications such as automotive, aerospace and medicine
    • Use IST(In-System Test)controller through IJTAG network
    • To access the chip during operation
  • Scan(Advanced DFT skill)
    • Scan test for improved test coverage for lower DPPM
    • Stuck-At, Bridge, Transition, Path-delay, OCCT, Burn-in
  • Boundary Scan
    • Inter-chip connection test method for system level testing
  • Physical DFT consider
    • Physical Reordering and Repartitioning

Physical Design

  • Accurate and robust timing analysis
    • LVF based variability library
    • Moment-based LVF to cope with non-Gaussian effect
    • Parametic OCV method
    • CCS/CCSN-based STA
    • Statistical Rvia STA
    • NP-Skewed corner STA for hold timing, min-pulse, and DCD check only
  • Physical Optimization
    • BEOL-aware delay optimization(BEOL resistance increase impacting path delay)
    • Mixed DDB/MDB Flow
  • Physical-aware Timing ECO
    • Minimize physical side-effect for ECO
  • MIM-aware Timing ECO
    • Produce a single ECO file for Multiply Instantiated Module
    • Accelerate multi-core CPU/GPU timing closure

Low Power

Dynamic Power Optimization

    • Multi-supply Voltage&Voltage Island
    • In-Ruch Current prevented power gating
    • Clock/Memory-Gating
    • Dynamic Voltage Frequency Scaling
    • Vector-Driven Optimization
    • Decap pre-placement method
    • Merge or split ICG/Multi-bit flip-flop
    • LowPower CTS(Concurrent Clock and Data Optimization)

Leakage Power Optimization

    • Multi-Vth Optimization
    • Gate-Length Biasing
    • Sign-off Leakage Optimization

Low Power Verification

    • Low power static rule check
    • Power-aware Somulation
    • Power-aware equivalence check

Power & Signal Integrity

Power Integrity Solution

    • Power Plan based on Early Prototyping Analysis
    • Dynamic Voltage Drop Analysis
    • Static Power Analysis
    • Power EM/BUMP Current
    • P/G Resistance check

Signal Integrity Solution

    • Signal EM
    • Glitch Noise analysis
    • Clock Jitter validation
    • Duty-cycle distortion methodology
    • Clock Propagation Check
    • 3-row decap inverter on CTS